The present invention relates to a semiconductor memory device, and more particularly to a read circuit for use in a multi-port memory device. The multi-port memory device including a plurality of ports employs a serial input/output (I/O) interface for processing a multiple concurrent operation with external devices.
Generally, most memory devices including random access memory (RAM) have a single port with a plurality of input/output pin sets. That is, the single port is provided for data exchange between a memory device and an external chipset. Such a memory device having the single port uses a parallel input/output (I/O) interface to simultaneously transmit multi-bit data through signal lines connected to a plurality of input/output (I/O) pins. The memory device exchanges data with the external device through a plurality of I/O pins in parallel. The I/O interface is an electrical and mechanical scheme to connect unit devices having different functions through signal lines and transmit transmission/reception data precisely. An I/O interface, described below, must have the same precision. The signal line is a bus to transmit an address signal, a data signal, and a control signal. A signal line, described below, will be referred as a bus.
The parallel I/O interface has high data processing efficiency (speed) because it can simultaneously transmit multi-bit data through a plurality of buses. Therefore, the parallel I/O interface is widely used in a short distance transmission that requires a high speed. In the parallel I/O interface, however, the number of buses for transmitting I/O data increases. Consequently, as distance increases, the manufacturing cost increases. Due to the limitation of the single port, a plurality of memory devices is independently configured so as to support various multi-media functions in terms of hardware of a multi-media system.
FIG. 1 is a block diagram of a conventional single port memory device. For convenience of explanation, a conventional ×16 512 M DRAM device as the single port memory device is illustrated.
The ×16 512 M DRAM device includes a plurality of memory cells, first to eighth banks BANK0 to BANK7, a single port PORT, and a plurality of global input/output (I/O) data buses GIO. The plurality of memory cells is arranged with a plurality of N×M memory cells having a matrix form, M and N being positive integers. The first to eighth banks BANK0 to BANK7 includes a row/column decoder for selecting a specific memory cell by row and column lines. The single port PORT controls signals inputted from or outputted to the first to eighth banks BANK0 to BANK7. The global I/O data buses GIO transfers signals between the single port and the banks, and between the single port and input/output (I/O) pins. Referring to FIG. 1, the global I/O data buses GIO include a control bus, fifteen address buses and sixteen data buses.
As described above, the single port memory device includes only a single port with a plurality of I/O pin sets for transferring data signals between the single port memory device and external devices via an external chipset. In the single port memory device, it is difficult to implement various multimedia functions because the single port memory device uses only one port. To implement the various multimedia functions in the single port memory device, each DRAM device has to be constituted independent of each other so as to perform its unique function. When the DRAM devices are constituted independent of each other, it is difficult to allocate a proper memory amount between memory devices based on the number of access times. As a result, an efficient utilization of the whole memory device is decreased.
FIG. 2 is a block diagram of a multi-port memory device disclosed in commonly owned co-pending application, U.S. patent application Ser. No. 11/528,970, filed in the USPTO on Sep. 27, 2006, entitled “MULTI-PORT MEMORY DEVICE WITH SERIAL INPUT/OUTPUT INTERFACE”, which is incorporated herein by reference.
For convenience of explanation, the multi-port memory device having four ports and eight banks is illustrated. Particularly, it is assumed that the multi-port memory device has a 16-bit data frame and performs a 64-bit prefetch operation.
As shown, the multi-port memory device includes first to fourth ports PORT0 to PORT3, first to eighth banks BANK0 to BANK7, first and second global input/output (I/O) data buses GIO_OUT and GIO_IN, and first to eighth bank control units BC0 to BC7. Each of the ports PORT0 to PORT3 located at a center of the multi-port memory device is arranged in a row direction, and performs a serial data communication with its own external device. The first to eighth banks BANK0 to BANK7 are classified into upper banks BANK0 to BANK3 and lower banks BANK4 to BANK7 based on their relative location with the first to fourth ports PORT0 to PORT3. The first global I/O bus GIO_OUT is arranged in the row direction between the upper banks BANK0 to BANK3 and the first to fourth ports PORT0 to PORT3, and transmits output data in parallel. The second global I/O bus GIO_IN is arranged in the row direction between the lower banks BANK4 to BANK7 and the first to fourth ports PORT0 to PORT3, and transmits input data in parallel. The first to eighth bank control units BC0 to BC7 control a signal transmission between the first and second global I/O buses GIO_OUT and GIO_IN and the first to eighth banks BANK0 to BANK7. The multi-port memory device further includes a phase locked loop (PLL) circuit 101 between the second and the third ports PORT1 and PORT2. The PLL circuit 101 is provided for controlling input/output timings of internal commands and data input to the first to fourth ports PORT0 to PORT3.
As described above, the multi-port memory device includes a plurality of ports, i.e., PORT0 to PORT3. Each port included in the multi-port memory device operates independently. Therefore, the multi-port memory device is widely employed for digital devices which process several processes concurrently.
FIGS. 3A to 3F are frame formats of serial signals used for a data transmission of the multi-port memory device shown in FIG. 2. FIG. 3A is a basic frame format; FIG. 3B is a write command frame format; FIG. 3C is a write data frame format; FIG. 3D is a read command frame format; FIG. 3E is a read data frame format; and FIG. 3F is a command frame format.
As an example, the read command frame shown in FIG. 3D is described in detail.
Referring to FIG. 3B, the write command frame is a unit of 20-bit serial signals. 18th and 19th bits PHY among the 20-bit serial signals correspond to a physical link coding bit, a 17th bit CMD means a command start point, a 16th bit ACT means an internal active state, a 15th bit WT corresponds to an internal write command, a 14th bit PCG means an internal inactive state, and a 13th bit RD means an internal read command. For example, during a normal read operation, 17th to 13th bits become “10001”. During an auto-precharge read operation, 17th to 13th bits become “10011”. A 12th bit ESC is a command expand information. By using the ESC bit, it is possible to perform a precharge operation and an auto refresh operation for all banks in the device. A 11th bit ABNK is an active bank information which is set while the RD bit is set. A 10th bit RFU is set while being ignored by the memory. 9th to 6th bits BANK have a bank information where the read operation is performed. 5th to 0th bits have a column address information.
The serial signals, having the frame format shown in FIGS. 3A to 3F, outputted from the plurality of the ports PORT0 to PORT3 are possible to access to every bank control units BC0 to BC7. Therefore, a clear definition for adjusting a transmission of the serialized signals is required for reliable data transmission of the multi-port memory device.